A custom layout of a 8 bit RISC microcontroller.

摘要

This thesis work presents custom layout of a 8-bit RISC microcontroller based on general architecture of the PIC 16f54 on AMI 0.6 submicron technology. The system designed is operative on all 33 general instructions of PIC 16f54 microcontroller. A modified architecture for branching is implemented. SRAM cells were used as general purpose memory. The operating frequency of the chip after simulation was 71.42 MHz (14nS clock period).; This thesis also discusses the detailed system analysis and circuit behavior of the microcontroller. An 8-bit Arithmetic Logic unit, 32 word SRAM array, 12-bit wide Input Output port, two layered stack segment, a free running counter and its timer module were all custom designed using Cadence's Virtusio Integrated Circuit Design environment to maximize speed. Conditional branching instructions were reduced to a single cycle, one cycle less than the PIC 16f54 microcontroller. A complex three phased clock was used for non-pipelined design. A simulated version of the microcontroller was tested fully in the IRSIM simulator. Detailed simulation results are presented and discussed.