首页> 外文会议>Conference on Advances in Patterning Materials and Processes XXXIV >Line End Shortening I so-Dense Etch Bias Improvement by ALD Spacer Shrink Process
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Line End Shortening I so-Dense Etch Bias Improvement by ALD Spacer Shrink Process

机译:线路结束缩短和我如此密集的蚀刻偏置通过ALD垫片收缩过程改进

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Multiple patterning employing etch shrink extends the scaling of hard mask open CD (HCD) to sub-50nm regime. A plasma-assisted shrink technique is primarily used in the back-end-of-line (BEOL) however it faces major challenges such as the line end shortening (LES) and large critical dimension iso-dense bias (IDB). In order to mitigate these two problems we apply an atomic layer deposition (ALD) spacer shrink process at 10nm metal interconnect layer with sub-20nm minimum half-pitch. As a result we observed 8nm LES improvement in tip-to-tip (T2T) two-dimensional (2D) structures, and 40% IDB reduction in one-dimensional (1D) structures. These improvements suggest that the ALD spacer shrink can contribute to more precise CD control in multiple patterning.
机译:使用蚀刻缩小的多个图案化将硬掩模打开CD(HCD)的缩放扩展到子50nm制度。等离子体辅助收缩技术主要用于线后端(BEOL),但是它面临着主要的挑战,例如线条缩短(LES)和大的临界尺寸异密偏压(IDB)。为了减轻这两个问题,我们将原子层沉积(ALD)间隔物收缩处理在10nm金属互连层中,具有Sub-20nm最小半间距。结果,我们观察到尖端尖端(T2T)二维(2D)结构的8nm LES改善,以及一维(1D)结构的40%IDB减小。这些改进表明,ALD垫片收缩可以有助于多图案中的更精确的CD控制。

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