Energy Efficient Decoder Circuit Using Source Biasing Technique in CNTFET Technology

摘要

VLSI technology is essential for chip fabrication, and 3 to 8 decoder circuits are used in electronic gadgets; consistency of design, small, fast, in this proposed circuit, 3 to 8 decoder is implemented using 20nm CNTFET technology. 3 to 8 decoders are the key segments in some real-time applications. For the most recent couple of years, the minuscule size of MOSFET, which is under many nanometers, made some operational issues, for example, expanded entryway oxide leakage, intensified intersection leakage, high sub-limit conduction. The proposed model is recreated utilizing Cadence virtuoso with 20nm CNTFET nodes.