Implementation of a Parallel Prefix Adder Based on Kogge-Stone Tree

摘要

Binary adder is an important module for microprocessors. We present a novel structure of binary adder, named Hyper-Parallel Prefix Adder (HPPA) in this paper. The basic idea of HPPA is to divide the addition into two levels, both of which are parallel prefix adder architecture. It can perfectly reduce the delay of wire loads by reducing the wire length in the critical paths; hence the performance of the adder can be significantly improved. Moreover, we present an optimized carry tree structure which is based on Kogge-stone tree named Grouped-Kogge-Stone tree (GKS tree), which has small nodes especially in the top level. Combining HPPA with GKS tree, we designed and implemented a 64-bit full adder. At the top level, we divide the two 64-bit addition operands into 8 groups, each of which is 8-bit. At the bottom level, we divide each 8-bit group into 4 equal sub-groups. Both of the two levels are composed of parallel prefix adders based on Grouped-Kogge-Stone tree. We design the adder using Verilog HDL to verify the performance. We have implemented the adder under 0.13μm CMOS process. Simulation results show that the maximal delay of the proposed adder layout is 578ps with the average power of 18.3mW.