Low power adiabatic 4-Bit Johnson counter based on power-gating CPAL logic

摘要

This In this paper, a different power saving adiabatic 4-bit Johnson counter based on two-phase CPAL circuits with power gating method is proposed. The power dissipation of proposed adiabatic Johnson counter comes out to be 16.3μW, 10μW, 9.2μW, 5.6μW and 10.9μW for frequencies 5MHz, 10MHz, 20 MHz, 50 MHz and 100MHz respectively with a load capacitance of 10fF. Proposed design saves more power in comparison to CMOS logic in frequency range of 5MHz to 100 MHz. Further, the basic gates using two phase CPAL circuits have been designed and simulated. The designed circuits are simulated in Tanner ECAD tool with 90nm technology.