In order to implement the high-resolution video coding, ITU-T puts forward a new coding canonical algorithm HEVC/H.265. Compared to a previous generation of video coding standard H.264, HEVC improvement to the motion estimation algorithm increases the complexity of this arithmetic unit, and leads to realtime processing being difficult in the existing platform. So using a hardware circuit to accelerate motion estimation becomes a key method of solving this problem. Based on previously studied hardware structure, this paper proposes 1-D systolic architecture that is suited to the HEVC motion estimation application. It is proved by experiments that compared to current motion estimation architecture, this architecture has the ability to improve hardware efficiency by 20% and realize more complex motion segmentation mode.
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