Design and Implementation of Parallel LVDS based on RapidIO

摘要

Designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, RapidIO Interconnect Architecture is a high-performance, packet-switched interconnect technology, where parallel Low-Voltage Differential Signaling (LVDS) is used. This paper first gives a brief introduction on the features of LVDS, and then presents a method to implement the parallel LVDS in the parallel RapidIO protocol using CPLD device and VHDL language; followed by a detailed discussion on the data line transmission errors generated during the process of high-speed data transportation due to the clock-data skew and the difference between transmission lines. A logical component, 4-bit-channel aligner, is developed to solve this sort of transmission errors. Finally a verification circuit board is developed to evaluate the implementation of parallel LVDS data transmission.