A real-time Stirling formula algorithm based on hardware acceleration is proposed. The large number is represented by the extended floating-point in the hardware design, and the hardware logic implementation for the Stirling formula is derived. By calculating the base 2 logarithm of the integer part and the fractional part, the result of the Stirling formula is divided into exponent and mantissa. The logarithm is derived by CORDIC, and the Taylor series is used to calculate the fractional power of 2. The proposed algorithm is implemented in FPGA, while the hardware block diagram and resources costs are deduced. The factorial results calculated by Matlab and FPGA based on the Stirling formula are compared and analyzed, while the proposed provides high accuracy and computing efficiency.
展开▼
