Power Efficient Code Converters Using Adiabatic Array Logic

摘要

Adiabatic logic brings about a great deal of power minimization in digital circuits. An application of the same is presented here by proposing a new design of some code converters-BCD to Excess-3, Binary to Gray and Gray to Binary, using the Adiabatic Array Logic. The proposed circuits show lesser power dissipation than the conventional static CMOS logic style and Two Phase Clocked Adiabatic Logic (2PASCL). The simulation is carried out in NI-Multisim software at 0.18μm, 1.8V CMOS standard process technology over a frequency range of 200-800MHz.