Using Register Design Tools to Sync Hardware/Firmware Designs - (PPT)

机译：使用寄存器设计工具来同步硬件/固件设计 - （PPT）

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Consequences: Hardware/firmware integration delays stretch into months. Chip respins cost USD $1,000,000 and 3 months. Firmware workarounds are complicated and bug-prone. The final product has inferior quality. Customer shipment is delayed.

机译：后果：硬件/固件集成延迟延迟到几个月。芯片重新征收费用US $ 1,000,000和3个月。固件解决方法很复杂，易于错误。最终产品质量较差。客户装运延迟。

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《Embedded Systems Conference India》|2013年||共20页
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作者
Gary Stringham;
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原文格式 PDF
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中图分类 TP311.5-53;
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Using Register Design Tools to Sync Hardware/Firmware Designs - (PPT)

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