Strain-Enhanced Performance of Si-Nanowire FETs

摘要

The combination of a multi-gate architecture and strain engineering is a promising way to fabricate high performance CMOS transistors. In this work we examine the effect of strain in Si nanowire Tri-Gate and Ω-Gate transistors. We present and discuss the results of electrical characterization of these advanced devices, with special attention to the carrier mobility, and to the piezoresistive coefficients.