VOID REDUCTION STRATEGY FOR BOTTOM TERMINATION COMPONENTS (BTC) USING FLUX COATED PREFORMS

摘要

As power density in semiconductors rises year-over-year, increased efficiency and reliability of Bottom Terminated Components (BTC) packages like QFN, LCS, QFP, and DPAK are becoming much more difficult to manage using traditional soldering techniques. The most notable method for thermal management of BTCs is to increase the efficiency of the thermal path through the bulk solder by decreasing the voids in the solder joint. The most recent surge in increased performance has driven many manufacturers to adjust their void requirements under BTCs from less than 25% to less than 15% or even 10% in many cases. Both the increased demand on the solder material performance and the ineffectiveness of traditional methods for addressing voiding have the market looking for new technology that can provide economical, reliable and repeatable results. There are several different approaches to reduce voiding: solder paste chemistry modification, stencil design, reflow profile optimization, and adding solder preforms to increase solder volume. No one approach has proven to provide an all-inclusive solution. Most recent work has demonstrated that using a unique void reduction technology (VRT) can significantly reduce voiding consistently and effectively. A collaboration between three companies representing solder materials (Alpha Assembly Solutions), power semiconductor component manufacturer, and an OEM of specialized test and measurement equipment (Rohde & Schwarz) worked together to investigate the effectiveness of solder preforms at reducing voiding under BTCs. The effects of factors such as component type and size, finish on PCB, preform types, stencil design, reflow profile and atmosphere, were studied using lead-free, low voiding, SAC305 solder paste and preforms.