Power efficiency of 3D vs 2D ICs

摘要

3D integration is considered as one of the most promising solutions to improve energy efficiency of heterogeneous ICs. We use floorplannning tools to evaluate power consumption related to inter-block connections for digital ICs implemented as 2D and 3D systems. We focus on 3D stacking using through-silicon-vias (TSVs). We evaluate contributions of wires, buffers and TSVs based on information available on the floorplannig level that include netlist, and positions of circuit blocks and TSV islands. Our results show that reduction in dynamic power could be achieved.