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Towards more Dependable Verification of Parameter Variations using Semi-Formal Techniques

机译:利用半正式技术朝着更可靠的参数变化验证

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Robustness of Analog/Mixed-Signal Systems against parameter variations is a key challenge. In analog components, but as well in DSP algorithms, parameters cannot be reproduced accurately. Parameter variations can lead to smaller or larger deviations of intended ('ideal') system properties. Depending on the inherent robustness of a design, system properties can leave the specified ranges. Unfortunately, verification of robustness of complex, heterogeneous system with many parameter deviations is a challenge. In this paper we describe a methodology for semi-symbolic verification that combines assertion-based methods for specification with semi-symbolic simulation. By assertions, we can describe the intended behaviour including particular analog behaviour and its deviations in a formalized way. By semi-symbolic simulations we can significantly increase coverage and dependability of the verification. The applicability and efficiency of the method is illustrated through a superheterodyne receiver.
机译:模拟/混合信号系统对参数变化的鲁棒性是一个关键挑战。在模拟组件中,但在DSP算法中,不能准确地再现参数。参数变化可能导致预期(“理想”)系统属性的更小或更大的偏差。根据设计的固有稳健性,系统属性可以留下指定的范围。不幸的是,核实复杂的鲁棒性,具有许多参数偏差的复杂的异构系统是挑战。在本文中,我们描述了一种用于半象征性验证的方法,该方法将基于断置的方法与半象征性模拟相结合。通过断言,我们可以描述包括特定模拟行为的预期行为及其以形式化的方式偏差。通过半象征性模拟,我们可以显着增加验证的覆盖率和可靠性。该方法的适用性和效率通过超外差接收器示出。

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