Optimization of the Binary Adder Architectures Implemented in ASICs and FPGAs

摘要

In this paper both theoretical and experimental comparative performance analysis of several binary adder architectures is performed. Also, one modified carry-bypass technique for adder performance improvement is presented. When applying simple unit-gate theoretical model for area and delay estimation it has been shown that logarithmic delay architectures (carry-lookahead and prefix adders) are the fastest but the most hardware demanding. On the other hand, the implementations in modern Virtex-6 general purpose FPGAs witness that here presented carry-bypass technique is the best tradeoff for such devices in terms of area, speed and power consumption. Presented results can be considered as a valuable resource in the selection of the most appropriate adder topology that will be used to implement a given arithmetic operation in a specified technology.