Development of 5-bit, 4-Inputs PWM Generator on FPGA through VHDL Programming

摘要

Pulse Width Modulation (PWM) generator is used to generate modified output duty cycle based on inputs applied. The duty cycle of a machine or system is the time it spends in an active state as a fraction of the total time under consideration. The main objective of this project is to design a PWM generator concept starting from three main components;; modulation signal, carrier signal and comparator, combined altogether to simulate a PWM structure through VHDL programming. The PWM structure will be implemented on FPGA for testing and further applications. This paper focuses on the development of an automatic PWM generator using VHDL which includes the design, functional/timing simulation and waveform analysis of every corresponding component of the design. The PWM generator has been successfully developed and simulation results and analysis have proven that the design satisfies the theoretical hypothesis.