Design of Driving Circuit of Area Array CCD with Interline Transfer Based on FPGA

摘要

In this paper, FPGA is chosen as the hardware design platform, on the base of sufficient analysis of ICX204AL's working principle and driving timing, the driving timing of CCD is described with Verilog HDL in the development environment of Quartus II 9.0. Finally, Modelsim SE 6.4a is employed to carry on the simulation to verify the accuracy of the design. The result shows that the driving circuit design can meet the demands of ICX204AL, and the CCD can work stably.