VHDL code generation based on a hierarchical node structure

摘要

This paper presents a VHDL code generation algorithm based on a hierarchical structure of elements provided by a graphical design tool that allows the design and simulation of VLSI dedicated microcontrollers. The control algorithm is designed visually using a software application based on the concept of logic neural networks [1]. Once the algorithm is implemented using the design tool, structured VHDL code [4] is generated using the same application based on the algorithm described in this paper. The generated code can then be downloaded into a dedicated VLSI device.