OPTIMIZING SOLDER VOIDS PERFORMANCE AT THERMAL PAD AND PRINTABILITY OF ITS PERIPHERAL PADS FOR DUAL ROW QFN ASSEMBLY

摘要

Thermal pad voiding control at QFN assembly is a major challenge due to larger coverage area, number of via and standoff height. In order to effectively remove the heat from the package and to enhance electrical performance, the die paddle needs to be soldered to the PCB thermal pad with minimum voids. Therefore, a good ground pattern helps in the outgassing process during the reflow process to prevent defects such as splatter, solder balling, and solder shorts. Voids within solder joint under the exposed thermal pad can have adverse effect on high speed and RF application as well as thermal performance. Voids within this ground plane can increase the current path of the circuit and also produce spot overheating. Therefore, both design and process were examined to minimize and control the voiding as well as printability of its peripheral pads. A simple DOE with a test board was design to investigate the effect of QFN peripheral pad land pattern, stencil thickness, thermal via density, partitioning of large thermal pad by a number of solder mask segments, and thermal pad paste pattern on the solder voiding performance. For subdivided thermal pad by solder mask (SMD) segment, the SMD system is more favorable than the subdivided by stencil aperture pattern, with the latter suffering more voiding due to poorer venting capability. Meanwhile, the number of thermal via found did not have any impact on the voiding performance. The voiding performance was further characterized through 3D X-ray inspection system.