Low-jitter frequency-modulated PLL: Clipped-FM PLL significantly reduces the maximum time interval error for proper operation of asynchronous serial data interfaces

摘要

Frequency modulation of a clock is a well-known and efficient way to spread clock harmonics around a center frequency, thus reducing emitted narrow-band RF energy. While smoothly changing the clock periods, modulation continuously shifts the clock edges back and forth over a time interval determined by the modulation frequency. The resulting time interval error compared to an unmodulated clock may get so large that it violates the specification of commonly used asynchronous data protocols. This paper describes a modulation technique which manages to minimize the time interval error using a single modulated PLL clock. As a prove of concept, measurement results for jitter, electromagnetic emission and CAN communication are added and discussed.