A design methodology for a low power bang-bang all digital PLL based on digital loop filter programmable coefficients

摘要

The implementation of bang-bang all digital phase locked loop (BBADPLL) in frequency synthesizer has proven a reduction in the power and, area. This reduction results from eliminating the need for complex, power, and area hungry blocks, such as an analog to digital converter (ADC) or a time to digital converter (TDC). These blocks are typically used to convert the average analog output to digital bits for the digital controlled oscillator (DCO). However, the non-linearity of the BBADPLL makes the traditional Laplace transform used in modeling the PLL invalid. Hence, there are serious design challenges in managing the tradeoffs between tracking bandwidth, jitter, and lock time. In this paper, a new design methodology that adjusts the digital loop filter (DLF) coefficients according to the digital controlled oscillator (DCO) frequency step is presented. The DLF coefficients are used to control the closed loop dynamics of the PLL. Useful expressions that model the DLF are presented for the design and optimization of the programmable DLF coefficients.