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3D Interconnect: The Challenges Ahead

机译:3D Interconnect:未来的挑战

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摘要

3D package solutions now account for a significant portion (~20%) of all die area processed today. Most all of this is still assembled in standard package configurations (FBGA, SO, MicroSD, etc) using wirebond interconnect. This paper will look at the many current technologies that have been adopted to enable 3D, and understand what the next steps will be to enable true die to die interconnection in a cost effective manner. Recent examples of various technologies from Fan-out WL-CSP, TSV for image sensors and MEMS, and other 3D concepts will be shown to highlight advantages and disadvantages of these emerging technologies. Prismark's roadmap for 3D adoption will be compared to previous new technology roadmaps to demonstrate the history of older technologies' ability to hang on to market share.
机译:3D包装解决方案现在占今天加工的所有模具区域的重要部分(〜20%)。大多数所有这些都仍然以使用Wirebond互连在标准包配置(FBGA,SO,MicroSD等)中组装。本文将研究已采用的许多技术,以启用3D,并了解下一步将以成本有效的方式实现真实芯片以便互连。最近来自FAN-OUT WL-CSP,图像传感器和MEMS的TSV和其他3D概念的各种技术的示例将突出这些新兴技术的优缺点。 PrisMark的3D采用路线图将与以前的新技术路线图进行比较,以展示旧技术悬挂到市场份额的历史。

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