Smart Energy Management and Low-Power Design of Embedded Systems on Algorithmic Level for Self-Powered Sensorial Materials and Robotics

摘要

Today there is an increasing demand for miniaturized smart sensors embedded in sensorial materials and smart actuators in microsystem applications. Each sensor and actuator node provides some kind of sensor, electronics, data processing, and communication. With increasing miniaturization and sensor-actuator density, decentralized network and data processing architectures are preferred, but energy supply is still centralized. Using local energy-harvesting technologies a decentralized energy supply can be provided, too. Energy harvesting, for example using thermo- electrical sources, actually delivers only low electrical power, requiring 1. smart energy management on the consumer side controlling the energy consumption and 2. low-power design. We propose and demonstrate a design methodology for embedded systems satisfying low power requirements suitable for self-powered sensor and actuator nodes. This design methodology focuses on 1. smart energy management at runtime and 2. application-specific System-On-Chip (SoC) design at design time contributing to low-power systems on both algorithmic and technological level. Smart energy management is performed spatially at runtime by a behaviour-based or state-action-driven selection from a set of different (implemented) algorithms classified by their demand of computation power, and temporally by varying data processing rates. It can be shown that power/energy consumption of an application specific SoC design depends strongly on computation complexity. For example a PID controller used for feedback position control of an actuator requires basically only the P-part, the I- and D-parts only increase position accuracy and response dynamic which are selectable. Depending on the actual state of the system, and the actual and estimated future energy deposit, suitable algorithms can be selected and executed optimizing the Quality-of-Service (QoS) and the trade-off between accuracy and economy. Signal and control processing is modelled on abstract level using signal flow diagrams (Matlab & Simulink toolbox [2]). These signal flow graphs are mapped to Petri Nets to enable direct high-level synthesis of digital SoC circuits using a multi-process architecture with the Communicating-Sequential-Process model on execution level and the High-Level synthesis framework ConPro [1]. Power analysis using simulation techniques on gate-level is obtained from the Silicium Compiler and Analyzer SiCA providing input for the algorithmic selection during runtime of the system leading to a closed-loop design flow. Additionally, the signal-flow approach enables power management by varying the signal flow rate which will be discussed later.