Designers of electronic packages and electronic circuits require besides thermal optimization also lifetime models for electrical and thermal vias and plated through holes respectively to obtain a reliability estimate. Reliability depends on via-geometry and manufacturing process conditions which influence thermo-mechanical properties of board (e.g. visco-elasticity) and electroplated copper (e.g. yield stress). This information, however, is needed for a lifetime model and can only be obtained from thorough material characterisation and failure analysis. Common analytical methods for via testing are based on electrical resistance measurements, where the vias are organized in series (e.g. daisy chain structure, figure 1). This method has severe shortcomings, as a failed via is first detectable if the via is almost torn (figure 2, equation 1); cracks at room temperature are often not detectable (thermal switch problem).
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