Performance of Buffered Switch Architectures

摘要

The authors propose an enhancement to the Tagle-Sharma network, a high performance self routing fault tolerant switch fabric which employs an enhanced scheme of the banyan network. The enhancement incorporates a shared-buffer in each switching element (SE) of the network to handle evolving traffic in converged networks. Two buffering management schemes are also proposed: the first-in-first-out (FIFO) configuration which employs backpressure control flow mechanism and follows the FIFO policy in handling the buffer; and the look-ahead configuration which still follows all the features of the FIFO scheme but uses the buffer only when needed. Simulation experiments under uniform random traffic are performed to measure the throughput, and average transmission delay of the switching networks. The Tagle-Sharma network is compared with the parallel banyan and the Benes networks. The results suggest that providing small buffers in the SEs can significantly improve the throughput performance of buffered switch architectures. Tagle-Sharma switching network performs better than the other Multistage Interconnection Network (MIN) designs. Furthermore, the look-ahead configuration performs better than the FIFO scheme.