When high speed integrated digital circuits technology scales down from one node to the other as ITRS recommends, a significant gain is obtained on signal speed, consumption and area of CMOS transistors. Nevertheless a specific issue occurs from the 45 nm technology node. The obtained gain on active devices is foiled by an increase of interconnect propagation delays in the Back-End of Line (BEOL). This issue especially concerns relatively long (few hundred of mm) interconnects of the intermediate metal level. By introducing drivers (repeaters) in order to divide long interconnect in shorter sections and choosing optimal drivers sizes, speed can be maximized. This paper proposes a new optimal buffer sizing, and maximum length to be used for repeater networks, to optimize propagation delay for long interconnect of the 32nm technology, by taking into account, for the first time, the input transition time at each stage.
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