dIP: A Non-Intrusive Debugging IP for Dynamic Data Race Detection in Many-core

摘要

Traditional debug facilities are limited in providing debugging requirements for multieore parallel programming. Synchronization problems or bugs due to race conditions are particularly difficult to detect with software debugging tools. This work presents a fast and feasible hardware-assistant solution for many-core non-intrusive debugging. The key idea is to keep tracks of data accesses of shared memory areas and their lock synchronization activities by proposed data structures in proposed debugging IP (dIP). A page-based shared variable cache is provided to keep shared variables as long as possible, and an inexpensive pluggable off-chip RAM can eliminate the false-positive rate efficiently. To decrease the debugging traffic block, this work provides a thread library to specify shared memory/lock events and transmit those events to the dIP by a small proper hardware co-processor (eXtend dIP) of each core. Our experimental result shows the debugging traffic block (worse-case) by increasing cores, and adding tolerance buffers in XdIP can efficiently ease off. Moreover, thereal workloads (SPLASH-2, MPEG4, and H.264) are executed by the dIP non-instructive race-detection with only 4.7%～12.2% slow down in average. Finally, the hardware cost of dIP is also low when the growing of many-core.