Low power adaptive pipeline based on instruction isolation

摘要

One of the most effective techniques to reduce a processor's power consumption is to reduce supply voltage. However, reducing voltage in the context of parameter variations can cause circuits to fail. As a result, voltage scaling is limited by a minimum voltage, often called Vccmin, beyond which circuits may not operate reliably. In this paper, we propose an architectural technique that enables microprocessor to operate at low voltage, while maintaining high frequency operations based on instruction isolation. The instruction isolation scheme isolates the set of possible instructions that do not complete within the clock period at the scaled Vcc and avoids possible timing errors in the instructions by dynamically adapting the clock period. Compared to current design, our scheme enables extra 13% average power saving.