Effective implementation and efficient utilization of clock gating logic is a critical element for dynamic power optimization. In this paper we propose three new clock gating effectiveness metrics to assess the quality of clock gating. We then propose applications of these metrics combined with RT level activity profiles, that enable accurate power estimation at downstream physical design stages. The approach apart from providing power optimization quality assessment, also provides 10X improvement in power estimation cycle time. Results on a 65 nm design have been presented to prove the claim.
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