According to the ITRS [1], MOS transistors will have gate lengths of around 10 nm in 2015, enabling the realization of very high performance VLSI circuits. For sub-32 nm generations, triple-gate field-effect transistors like FinFETs constitute a possible option as well as FD-SOI and planar DG-MOSFETs due to their immunity to short channel effects (SCE) and proximity to standard bulk planar CMOS processing [2-7]. Nevertheless, FinFET architecture could suffer from some specific technological limitations related to Fin patterning, gate stack and junction conformality, as well as spacer and source/drain engineering. In this work, a detailed electrical characterization of advanced triple-gate FinFETs has been carried out focusing on mobility extraction at short gate length and narrow Fin effects. Low temperature measurements (100-300K) and interface quality determination by LF noise analyses have also been performed for better physical insights.
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