FPGA Implementation of BP-DF-MPIC Detectors for DS-CDMA Systems in Frequency Selective Channels

摘要

Multistage parallel interference cancellation (MPIC) based detectors allow to mitigate multiple access interference and intersymbol interference in direct-sequence code division multiple access (DS-CDMA) systems. Better performance is obtained when decision feedback (DF) is employed. Although MPIC and DF-MPIC have the same arithmetic complexity, DF-MPIC needs much more FPGA resources when compared to MPIC without decision feedback. Block parallel DF-MPIC (BP-DF-MPIC) had been proposed in frequency nonselective channels allowing better tradeoff between performance and FPGA area occupancy. In this paper, FPGA implementation of BP-DF-MPIC in frequency selective (FS) channels is proposed. To reach a bit error rate of 10~(-2), BP-DF-MPIC shows a 4dB improvement over the MPIC without decision feedback with only 18.3% increase in FPGA resources compared to 77.5% for DF-MPIC.