The IAEA Universal Nondestructive Assay Data Acquisition Platform (UNAP)

摘要

The Universal NDA Data Acquisition Platform (UNAP) will be the next generation data acquisition system for the International Atomic Energy Agency (IAEA) attended and unattended non-destructive assay measurement equipment. The system will also be the principal data acquisition module for the Japan Nuclear Fuel Limited (JNFL) MOX Fuel Fabrication Plant (J-MOX) safeguards project. The primary goal of the UNAP development is for the new module to become the IAEA standard and replace existing Non-Destructive Assay (NDA) modules such as the JSR-12, the MiniGrand, the Advanced Multiplicity Shift Register (AMSR), and the JSR-14. The inputs to the UNAP will be a superset of the existing inputs of all these previous modules with flexibility to anticipate future developments. The core measurement capabilities of the UNAP include three multiplicity shift registers clocked at 50MHz, an eight channel combination scalar-derandomizer with output to one of the shift registers, dual current mode measurement channels with 30 femtoampere resolution, a list mode channel with 100 nanosecond resolution, four programmable threshold single channel analyzers (SCA), a 4-20mA channel, and several discrete digital inputs and isolated contact closure outputs. All measurement data is acquired and reduced by a Freescale PowerQUICC processor and is locally stored in a 16GByte solid state drive. The UNAP will authenticate and encrypt the data for transmission across the 100BaseT Ethernet interface to the data acquisition system. The instrument has three external 100BaseT ports connected through an internal switch to allow daisy chaining multiple UNAPs or direct connection to other Ethernet devices such as surveillance cameras. The UNAP includes three USB ports for access to the security dongle containing the tokens, connection to a USB memory drive, and for connection to plug and play USB devices for pass through control and collection from the data acquisition system. The UNAP has been architected around the commercial standard Compact Peripheral Component Interface (cPCI) bus which is prevalent in the military and space avionics industry. The 32-bit 33MHz cPCI bus has a peak 132Mbyte/sec data transfer rate and provides the interface between the processor board and the UNAP Data Acquisition board (UDA). This separation of functionality has allowed for a parallel development of the two principle boards, reducing both development cost and schedule. The cPCI bus is implemented on a 2-slot rigid backplane with flex-PCB extensions for the external interconnects directly to the UNAP enclosure. To increase robustness, all I/O on the two cPCI boards is through the backplane on unused pins. The Dual Current Mode (DCM) femtoammeter capability is provided on an additional PCB housed within a fully shielded enclosure inside the UNAP chassis. This DCM module includes the two femtoammeter channels, a negative 300V programmable bias supply, and a digital interface to the UDA board through the flex-PCB backplane. Also enclosed within the UNAP chassis are a programmable 2000V power supply for biasing 3He detectors, a low voltage power supply, and a lithium-ion battery with associated charging circuitry to provide 25 hours of operation during unforeseen power outages. The embedded PowerQUICC processor will operate on a realtime variant of Linux on the solid state drive. Also stored on the solid state drive will be the application code and the UNAP configuration table. All UNAP operating information such as thresholds, bias voltages, shift register gate widths, and trigger conditions will be stored in the configuration table. The operating system, application code, and configuration table can be updated or modified through authenticated input from a USB memory stick. In addition, the configuration table can be modified or updated through authenticated input from the Ethernet port. The specification for the UNAP is complete and the design team from Los Alamos National Laboratory