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On the Correlation between Controller Faults and Instruction-Level Errors in Modern Microprocessors

机译:关于现代微处理器中控制器故障与指令级别错误的相关性

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We investigate the correlation between register transfer-level faults in the control logic of a modern microprocessor and their instruction-level impact on the execution flow of typical programs. Such information can prove immensely useful in accurately assessing and prioritizing faults with regards to their criticality, as well as commensurately allocating resources to enhance testability, diagnosability, manufacturability and reliability. To this end, we developed an extensive infrastructure which allows injection of stuck-at faults and transient errors of arbitrary starting point and duration, as well as cost-effective simulation and classification of their repercussions into various instruction-level error types. As a test vehicle for our study, we employ a superscalar, dynamically-scheduled, out-of-order, Alpha-like microprocessor, on which we execute SPEC2000 integer benchmarks. Extensive experimentation with faults injected in control logic modules of this microprocessor reveals interesting trends and results, corroborating the utility of this simulation infrastructure and motivating its further development and application to various tasks related to robust design.
机译:我们研究了现代微处理器控制逻辑中寄存器传输级别故障的相关性及其对典型程序执行流程的指令级别影响。这些信息可以在准确地评估和优先考虑其临界性方面的故障以及相应地分配资源以提高可测试性,诊断,可制造性和可靠性的情况下非常有用。为此,我们开发了一个广泛的基础设施,允许在任意起点和持续时间的故障和瞬态误差中注入困境和瞬态误差,以及成本效益的模拟和对各种指令级错误类型的影响分类。作为我们研究的测试车辆,我们使用Superscalar,动态预定,无序,alpha样微处理器,我们在其中执行Spect2000整数基准。广泛的实验在这种微处理器的控制逻辑模块中注入的故障揭示了有趣的趋势和结果,证实了这种模拟基础设施的效用,并激励其进一步的开发和应用于与强大设计相关的各种任务。

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