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Development of a Novel Cost-Effective Package-on-Package (PoP) Solution

机译:开发一种新颖的经济高效的包装包装(POP)解决方案

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Package-on-Package (PoP) is one of the major 3D packaging approaches. It vertically combines discrete memory and logic Ball Grid Array (BGA) packages, where one package rests on the top of another. Recently, PoP technologies have attracted more interests, especially for portable electronics related products and applications. For the existing PoP solutions, they have the following disadvantages: (1) As the next-generation PoP module incorporates more features, top package requires more memory inside and finer pitch is needed. Finer pitch of top package will translate into lower stand-off height between top and bottom packages. It means the mold cap of the bottom package should be kept as thin as possible. (2) The logic function of the bottom package will be expanded with two stacked dies. The mold cap of the bottom package should be thicker than that of the original design which has only one die inside. It causes the conflict between the stand-off height issue and expanded logic functionality. (3) The bottom package is a Plastic Ball Grid Array (PBGA) package format normally. Due to its partial mold-cap design, the package's warpage could be large especially non-uniform on a panel since the structure is not well balanced. (4) The bottom package with customized mold chase with the top pin gate molding method has the high cost issue. To solve the above disadvantages, ASTRI has developed a new PoP structure, which employs a new bottom package that is over molded Fine-pitch Ball Gird Array (FBGA) format with mechanically balanced package structure. For the top package, it's a commercial FBGA format with two die stacking inside. Since the new bottom package structure is based on an existing FBGA format, the mold chase is independent of the mold cap and size of the bottom PoP package. The final mold layer for bottom package has a thickness of 0.5mm. The top interface of the bottom PoP package has 136 pads with 0.65mm pitch and a two-row peripheral format, while the bottom interface has 272 pads with 0.65mm pitch and a four-row peripheral format. The size of both top and bottom packages is 14×14mm~2. The configuration of the package is evaluated by scanning electron microscopy (SEM), which shows a favorable interconnection structure. The warpage of the bottom PoP package after assembly process is characterized by shadow moire system. The warpage is well controlled by adopting the fully molded structure. The average value is around 30μm that is well below the warpage target of 80μm widely used in the industry.
机译:封装上封装(PoP)是主要的3D封装方法之一。它可垂直堆叠多层存储器和逻辑球栅阵列(BGA)封装,其中,在另一个的顶部一个封装休止符。近日,流行的技术吸引了更多的利益,特别是对于便携式电子产品相关的产品和应用。对于现有PoP解决方案,它们有以下缺点:(1)作为下一代的PoP模块具有更多的功能,顶部封装需要更多的内存内,并且需要更精细的节距。顶层封装的细间距将转化为较低的对峙,顶部和底部包之间的高度。这意味着底部封装的模具帽应保持尽可能的薄。 (2)底包的逻辑函数将具有两个堆叠裸片进行扩展。底部封装的模具帽应该比仅具有一个模具内的原始设计的厚度更厚。它使托起高度的问题,扩展逻辑功能之间的冲突。 (3)底部封装通常是一个塑料球栅阵列(PBGA)封装格式。由于其部分模具帽设计中,封装的翘曲可能较大特别不均匀一个面板上,因为该结构不能很好地平衡。 (4)底部封装与顶销栅极成型法定制的模套具有成本高的问题。为了解决上述缺点,ASTRI开发了一种新PoP结构,它采用了一种新型底部封装,其包覆成型精细间距球栅阵列(FBGA)格式与机械平衡的封装结构。对于顶包,这两个芯片堆叠内商业FBGA格式。由于新的底部封装结构是基于现有的FBGA格式,模套是独立于底层PoP封装的模具帽和尺寸。对于底包最终模具层的厚度0.5毫米。底部PoP封装的顶部界面具有136个垫与0.65mm节距和两行外围格式,而底部界面具有272个垫与0.65mm节距和四排外围格式。顶部和底部包的大小为14×14毫米〜2。封装的结构是由扫描电子显微镜(SEM),其显示了良好的互连结构进行评价。装配过程之后的底部PoP封装的翘曲的特征在于阴影莫尔系统。翘曲以及通过采用完全模制的结构来控制。平均值为30微米左右是远低于80微米的翘曲目标广泛用于工业。

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