Self-aligned Double-Gate (DG) Nanoscale Vertical MOSFET'S withReduced Parasitic Capacitance

摘要

Enhanced symmetrical self-aligned double-gate (DG) vertical nMOSFET with low parasitic capacitance is presented.The process utilizes the oblique rotating ion implantation (ORI) method combined with fillet local oxidation (FILOX)technology (FILOX + ORI). Self-aligned region forms a sharp vertical channel profile that increased the number ofelectrons in the channel. These have improved drive-on current and drain-induced-barrier-lowering (DIBL) effect with areduced off-state leakage current tremendously. The gate-to-drain capacitance is significantly reduced while having asmall difference of gate-to-source capacitance compared to FILOX device. The drain overlap capacitance is a factor of0.2 lower and the source overlap capacitance is a factor of 1.5 lower than standard vertical MOSFETs.