Power-delay efficient technology mapping of BDD-based circuits using DCVSPG cells

摘要

Efficient technology mapping has become an important vehicle in deep-submicron technologies for improving performance-oriented synthesis. On the other hand, library-based Pass Transistor Logic (PTL) synthesis, like Lean Integration with Pass-Transistors (LEAP) synthesis, has drawn significant attention to the VLSI research community. In this paper, we propose three new library cells based on Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG). Synthesis using these cells outperforms the existing LEAP-based synthesis for BDD-based (Binary Decision Diagram-based) circuits. Results on benchmark circuits show that the new cell-based mapping technique yields more than 60% reduction in both power and delay in the synthesized circuits.