Compiler technologies for mapping program code to high-performance, power-efficient programmable image processing hardware platforms

摘要

The method is described. The method includes compiling program code that is the target of an image processor having programmable stencil processors configured with respective two-dimensional execution lanes and shift register circuit structures. The program code is for implementing a directional acyclic graph and is comprised of a plurality of kernels to run on each of the stencil processors of the stencil processors, wherein the compiling comprises: a different number of kernels than the stencil processors in the image processor, And recognizing that the user is present in the user terminal; Recognizing that at least one of the kernels is more computationally intensive than the other of the kernels; And recognizing that the program code has resource requirements that exceed the memory capacity of the image processor. The step of compiling may comprise, in response to any recognition of the above recognition: horizontal fusion of the kernels; Vertical fusion of kernels; Splitting one of the kernels into multiple kernels; Space partitioning the kernel into a number of spatially partitioned kernels; Further comprising performing any of dividing the directed acyclic graph into smaller graphs.