An Efficient Programmable Logic Device Implementation of the Second-order Extended Physical Addressing

摘要

This paper describes an efficient Programmable Logic Device (PLD) implementation of the Second-order Extended Physical Addressing, connecting the microprocessor-based systems and the external peripherals. This addressing technique, based on the use of software/hardware systems and reduced physical addresses, enlarges the interfacing capacity of the microprocessor-based systems. The input of our system hardware part will be connected to the system bus. The output, which is a new bus, will be connected to an external device. To accomplish the bus communication, the hardware part realizes a conversion of system bus data into new bus addresses. Furthermore, the software part ensures the transfer, with distinct addresses, of the simple data and the data that is intended to be converted. The use of this system with three system addresses and N bit data bus gives a new bus with N bit data bus and 2{sup}(2N) physical addressing capacity.