Design, Analysis, and Characterization of Tri-Modal 12.8 Gbps Single-Ended and 20 Gbps Differential Memory Interfaces

摘要

In this paper, we present the design, analysis, and characterization of tri-modal parallel interfaces using single-ended and differential signaling offering data rates of 12.8 Gbps and 20 Gbps, respectively. These bidirectional memory interfaces also communicate with standard DDR3 and GDDR5 DRAMs at 1.6 Gbps and 6.4 Gbps, respectively with no package change. The interface is enabled by substantially sharing and reuse of the circuit elements between the signaling modes, particularly at the driver output stage and the clocking circuits. The two designs also incorporate stress protection mechanism that guards thin-oxide devices used in the high-speed mode against the high IO voltage of DDR3 and GDDR5 standards. The system uses asymmetrical architecture where the equalization and timing adjustment circuits for both memory WRITE and READ transactions are on the controller to reduce the memory cost. The analysis and optimization steps employed to mitigate the effect of inter-symbol interference, crosstalk, and supply noise are discussed. The effect of data encoding techniques on system timing margin is also investigated at a small incremental cost impact to the system. We further compare measured silicon data from the single-ended and differential interfaces. Several of the noise reduction techniques, such as coding and noise tracking, were also verified with measurement made on a prototype system. The interface consisting of 16 data links achieves efficiency of better than 5.0 m W/Gbps and 6.1 m W/Gbps for 12.8 Gbps single-ended and 20 Gbps for differential signaling, respectively.