Forward Error Correction (FEC) for High-Speed SerDes Link System of 25-28Gb/s

摘要

In this paper, we investigate the use of forward error correction (FEC) for a very high speed serial link system (25 to 28 Gb/s). Different FEC codes are analyzed and compared in terms of their coding gain, overhead, encoding and decoding delay, and complexity. Simulation and analysis show that FEC improves the bit error rate (BER) performance and system margin with moderate cost. As a post-processing stage, FEC provides a tradeoff to reduce the requirement for a complicated equalization scheme. Burst-error correcting FEC can improve the error detection capability of Cyclic Redundancy Checks (CRC) to reduce system error detection failure rate resulting from Decision Feedback Equalizer (DFE) error propagation. This paper shows that double burst error correcting FEC outperforms single burst error correcting FEC over long reach channels at 25 and 28 Gb/s. Double error correcting Reed-Solomon (RS) codes are studied for their coding gain, latency and decoding complexity. The possible usage of FEC scheme in industry standards such as 100 Gb/s Ethernet is also discussed.