Creating C++ IP for High Performance Hardware Implementations of FFTs

摘要

The increasing level of circuit integration is enabling the use of more complex digital signal processing algorithms in modern applications. The fast Fourier transform (FFT) is one the most widely used signal processing algorithms. There is no single hardware implementation that fits all needs and in fact higher performance FFTs are used in applications as it becomes feasible to do so. This paper presents a family of register based architectures that can be obtained from a highly parameterizable C++ specification. The size, numerical precision, radix algorithm and parallelism of both computation and I/O transfers are parameterized in the specification. Optimized RTL targeted to a specific ASIC or FPGA technology can be generated from that specification using a high-level synthesis (HLS) flow. The generated RTL is then verified against the original C++ specification using an automated verification environment.