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Progress towards Optical Interconnects for Intrachip Global Communication

机译:intachip全局通信光学互连的进展

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Microprocessor performance is now limited by the poor delay and bandwidth performance of the on-chip global wiring layers. Although relatively few in number, the global metal wires have proven to be the primary cause of performance limitations - effectively leading to a premature saturation of Moore's Law scaling in future Silicon generations. Building upon device-, circuit-, system- and architectural-level models, a framework for performance evaluation of global wires is developed aimed at quantifying the major challenges faced by intrachip global communications over the span of six technology generations. This paper reviews the status of possible intra-chip optical interconnect solutions in which the Silicon chip's global metal wiring layers are replaced with a high-density guided-wave or free-space optical interconnection fabric. The overall goal is to provide a scalable approach that is compatible with established silicon chip fabrication and packaging technology, and which can extend the reach of Moore's Law for many generations to come. To achieve the required densities, the integrated sources are envisioned to be modulators that are optically powered by off-chip sources. Structures for coupling dense modulator arrays to optical power sources and to free-space or guide-wave optical global fabrics are analyzed. Results of proof-of-concept experiments, which demonstrate the potential benefits of ultra-high-density optical interconnection fabrics for intra-chip global communications, are presented.
机译:微处理器性能现在受到片上全局接线层的延迟和带宽性能的限制。虽然数量相对较少,但全球金属线已被证明是绩效限制的主要原因 - 有效地导致摩尔在未来硅代的过早饱和。建立在设备,电路,系统和架构级模型上,开发了一种用于全球电线的性能评估的框架,旨在量化intachip全球通信面临的主要挑战在六个技术一代。本文综述了可能的内部光学互连解决方案的状态,其中硅芯片的全局金属布线层被高密度导向波或自由空间光学互连织物代替。总体目标是提供一种可扩展的方法,该方法与已建立的硅芯片制造和包装技术兼容,并且可以延长摩尔法的范围,以便许多几代人来。为了实现所需的密度,集成来源被设想为由片外源光学通电的调制器。分析了用于将致密调制器阵列耦合到光学电源的结构和自由空间或引导波光学全球织物。概念验证实验结果表明,展示了用于芯片内全局通信的超高密度光学互连织物的潜在益处。

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