Safe Interpolation Distance for VT5 Resist Model

摘要

As the technology shrinks toward 65nm technology and beyond, Optical Proximity Correction (OPC) becomes more important to insure proper printability of high-performance integrated circuits. This correction involves some geometrical modifications to the mask polygons to account for light diffraction and etch biasing. Model-based OPC has proven to be a convenient, accurate, and efficient methodology. In this method, raw calibration data are measured from the process. These data are used to build a VT5 resist model [1] that accounts for all proximity effects that attendant to the lithography process. To ensure the reliability of the calibrated VT5 model, these data must be broad in the image parameter space (IPS) to account for different one-dimensional and two-dimensional features for the design intent.Failure to provide sufficient IPS (i.e. mimic the design intent) coverage during model calibration could result in marginalizing the VT5 model during OPC, but is difficult to judge when there is enough data volume to safely interpolate and extrapolate design intent. In this paper we introduce a new metric called Safe Interpolation Distance (SID). This metric is a multi-dimensional metric which can be used to automatically detect the portions of the target design that are not covered well by the desired VT5 model.