Material Properties Of Epoxy Based Wafer Applied Coating Using A Novel Curative

摘要

Flip chip and chip scale packaging designs are bringing smaller and lighter devices to market, especially those that are portable and battery operated. The combination of environmental demands and increased performance requires a greater emphasis on efficient and effective package designs. Wafer level packages offer the hope of driving the pitch size of chip scale packages (CSPs) even smaller as the interposer of the CSP is eliminated. Wafer level chip scale packaging, (WLCSP) not only offers the advantage of economy of scale processing but also potentially improved yield as testing occurs at the wafer level, so known good pre-packaged die are only used in assembly. Further opportunities for wafer level packaging capabilities are being found in elements of stacked die packaging. While many wafer level packaging design elements exist, (e.g. redistribution layers, interposer layers, build up layers, etc.) wafer-leve-lapplied die protectants (so-called wafer lever underfills) have not seen successful commercialization. Wafer level underfills promise to meet the increasing performance and reliability demands of flip chips, while simultaneously decreasing processing costs. Sadly, neither promise has come true, and wafer level underfill demand remains elusive.