Fabrication of Nano-sized Single-walled Carbon Nanotube Vias for Electronic Device Applications

摘要

Vertically aligned single-walled carbon nanotubes (SWNTs) were synthesized at a low temperature of 600°C by radical chemical vapor deposition (CVD). For applying this technique to electronic devices, we synthesized SWNTs in nano-sized SiO_2 holes to fabricate SWNT-vias, which is expected to be used for multi-layer interconnects and vertically aligned field effect transistors (FET). SWNTs were grown in holes with various sizes and shapes patterned by electron beam lithography. We also show the concept of large area deposition of vertically aligned SWNTs by improved radical CVD system.