MRAM with stacks of electrically connected dual memory cells located between the write lines to produce by multiple logic states, had been proposed by Motorola[1] and HP[2]. In those cases, cells with different amplitude in coercivity, Hc, (or anisotropy) are used to enable writing of all the dual-bit memory states. Since the writing of the high Hc cell always overwrite the low Hc cell, the high Hc cell need to be written first follow by the writing of the low Hc cell. The situation is much worse when half selected cells are added into consideration. This paper address the issues of the current dual bit cell as well as provide an alternative design to alleviate the selective writing problem.
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