首页> 外文会议>Annual Interational Wafer-Level Packaging Conference >WAFER-LEVEL PACKAGING: EFFECTIVE COST REDUCTION WITH WAFER BONDING
【24h】

WAFER-LEVEL PACKAGING: EFFECTIVE COST REDUCTION WITH WAFER BONDING

机译:晶圆级包装:用晶圆键合的有效成本降低

获取原文

摘要

The market demands for ongoing price reductions in consumer electronics require novel and innovative manufacturing processes. Packaging of the devices is a major cost factor, and therefore continual reduction of the packaging costs is key. Wafer bonding enables first-level packaging on the wafer level, which has been introduced 15 years ago for automotive devices. Due to the very short product life cycles in consumer electronics, sometimes only a few months, the choice of the appropriate bonding method is driven by the potential for continual cost reduction. Depending on the product, innovative bonding processes using SU-8 and BCB, but also the established MEMS processes like metal-metal and direct bonding, can be the right choice. The decision criteria are: Highest yield on all manufacturing process is imperative. This involves not only the bonding process, most important pressure and temperature uniformity, but also the pre-processing steps like cleaning and plasma activation. Integration of the pre-processes in the wafer bonding platform enables real-time process control. Due to the accurate timing of the process flow the bonding process time can be optimized and the capacity and throughput are increased. Very high wafer-to-wafer alignment accuracy allows minimized substrate real estate consumption of the gasket enabling both, more chips per wafer and a higher production capacity. The SmartView alignment principle reduces the manufacturing steps, as no backside alignment keys are needed, and reduces the material costs as backside polished wafers are not necessary. Process compatibility between R&D and production equipment significantly reduces cost and time for process qualification. A modular and redundant equipment concept results in high uptime with no trade-offs. In this paper the technical differences for established and modern wafer bonding processes are reviewed. The impacting factors on cost reduction for current and upcoming product generations are analyzed in detail.
机译:对消费电子产品的持续降价的市场需求需要新颖和创新的制造过程。设备的包装是主要的成本因素,因此包装成本的持续降低是关键。晶圆粘接使第一级包装能够在晶圆水平上,这是在15年前推出的汽车设备。由于消费电子产品的寿命周期短,有时只有几个月,可以选择适当的粘接方法的选择是由不断降低成本的潜力。根据产品,使用SU-8和BCB的创新粘合工艺,也是金属金属和直接粘接等建立的MEMS工艺,可以是正确的选择。决策标准是:所有制造过程的最高产量是必要的。这不仅涉及粘合过程,最重要的压力和温度均匀性,而且还包括清洁和等离子体激活的预处理步骤。晶圆键合平台中预流程的集成可以实现实时过程控制。由于处理流程的精确定时,可以优化键合处理时间,并且增加容量和吞吐量。非常高的晶片到晶圆对准精度允许最小化垫片的基板房地产消耗,使得每个晶片更多的芯片和更高的生产能力。 SmartView对准原理降低了制造步骤,因为不需要背面对准键,并且降低了由于背面抛光晶片而不是必需的材料成本。研发和生产设备之间的过程兼容性显着降低了流程资格的成本和时间。模块化和冗余设备概念导致高正常运行时间,无权衡。本文综述了建立和现代晶圆粘合过程的技术差异。详细分析了对电流和即将到来的产品几代成本降低的影响因素。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号