Addressing DSM Design Risks With Mask-Less Structured ASICs

摘要

eASIC Corp. has developed a new Structured ASIC product line that dramatically reduces the development costs and time associated with ASIC development in Deep Submicron (DSM) technologies of 130nm and below. eASIC has created a silicon technology that uses a coarse-grained FPGA-style "universal logic cell" as the design primitive. These cells are packed into a regular array of cells, or 'sea-of-cells', that are routed with metal interconnect using a fabric of fixed routing segments. The connections of these routing segments are created through a single via layer in high-level metal that is configured using eBeam maskless lithography. The regular structure of the eASIC technology is ideally suited to address the issues associated with DSM lithography and fabrication. eASIC Corp. has developed the FlexASIC Structured ASIC family of devices based on eASIC technology. This family of pre-fabricated standard base arrays is designed as general-purpose configurable logic devices with the ease of use and prototype costs of FPGA design, but with speed, density, power consumption, and production costs comparable to standard cell design. This paper describes the technology and design flows of the FlexASIC, and provides a case study of a FlexASIC implementation of an SoC Processor reference design.