Two of the key factors needed to fabricate high yielding copper interconnect device structures are the selection of plating bath additives and developing plating parameters to promote bottom up growth. Activation of additives, especially accelerators, however, often produces undesirable over-plating at dense areas of the wafer containing sub-micron size structures. Depending on the interconnect design and metal deposition process, the within die over-plating range can easily exceed 20% of the nominal deposited film thickness. For high aspect ratio (AR) sub-micron size features, the over plating range may vary between 200 to more than 600nm. The additional CMP time and processes needed to clear the undesirable excess metal produce dishing and erosion defects which cause problems in immediate and subsequent interconnect levels on the *-" substrate. In this communication we describe methods to minimize over-plating and demonstrate an electrochemical method for controlling the v activities of the additives during metal deposition to effectively suppress over-plating without introducing other undesirable defects in the deposited metal.
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