Measuring S-parameter Models of Power Delivery Networks in FPGA Systems by Using an Embedded Multi-port Vector Network Analyzer

摘要

Power supply noise may create intermittent timing failures in FPGA logic core and jitter in the input/output (I/O) cells, which may produce failures at system level. Existing power integrity analysis tools use extracted models of the power delivery network (PDN) on die, package, and PCB to evaluate the power supply noise seen by active circuits. These tools work well in a custom integrated circuit design process where designers have full access to the schematic and layout design files of the die, package, and PCB. However, in an FPGA system design process there is no access to the schematic and layout design files of the FPGA die and FPGA package, limiting the power integrity analysis efficiency and increasing the chances of power supply noise induced intermittent failures at system level. This paper presents a novel method for power integrity analysis in FPGA systems by configuring the FPGA to function as a Vector Network Analyzer (VNA) test instrument for its own power delivery network. This embedded VNA measures the impedance profile of the PDN as seen by the logic circuits of the FPGA fabric, and extracts a complete S-parameter model of the power delivery network of the FPGA system, that includes the PDN elements on the FPGA die, FPGA package, and PCB. The S-parameter model can be then used in circuit simulation tools to evaluate the power supply noise in the FPGA logic core and the timing jitter in the FPGA I/O data links.